`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/4/8 22:42:14
// Design Name: 
// Module Name: send_fifo
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module send_fifo(
   input                        clk             ,
    input                       rst             ,
    input   signed[11:0]        send_data_r     ,   
    input   signed[11:0]        send_data_i     ,
    input                       send_zc_ena     ,
    input                       send_data_ena   ,
    input                       zc_from         ,
    output  signed[11:0]        send_get_r      ,
    output  signed[11:0]        send_get_i      ,
    output   reg                 fifo_rd_en=0     

	
    );

reg send_zc_ena_d;
always@(posedge clk)begin
    send_zc_ena_d<=send_zc_ena;
end
wire send_zc_from_fix;
assign send_zc_from_fix = ({send_zc_ena_d,send_zc_ena}==2'b10)? 1'b1:1'b0;
/*wire send_zc_from_fix_d;
delay_fifo_rst u_delay_fifo_rst (
  .D(send_zc_from_fix),      // input wire [0 : 0] D
  .CLK(clk),  // input wire CLK
  .CE(~rst),    // input wire CE
  .Q(send_zc_from_fix_d)      // output wire [0 : 0] Q
);
*/

//reg fifo_rd_en;
always@(posedge clk)begin
    if(rst)begin
        fifo_rd_en<=1'd0;
    end
    else begin
        if(zc_from)begin
            fifo_rd_en<=1'd1;
        end
    end
end

wire fifo_full,fifo_empty;
fifo_send2rebuild send_delay2rebuild_r (
  .clk(clk),      // input wire clk
  .srst(send_zc_from_fix||rst),    // input wire srst
  .din(send_data_r),      // input wire [11 : 0] din
  .wr_en(send_data_ena),  // input wire wr_en
  .rd_en(fifo_rd_en),  // input wire rd_en
  .dout(send_get_r),    // output wire [11 : 0] dout
  .full(fifo_full),    // output wire full
  .empty(fifo_empty)  // output wire empty
);

fifo_send2rebuild send_delay2rebuild_i (
  .clk(clk),      // input wire clk
  .srst(send_zc_from_fix||rst),    // input wire srst
  .din(send_data_i),      // input wire [11 : 0] din
  .wr_en(send_data_ena),  // input wire wr_en
  .rd_en(fifo_rd_en),  // input wire rd_en
  .dout(send_get_i),    // output wire [11 : 0] dout
  .full(),    // output wire full
  .empty()  // output wire empty
);




endmodule
